US 11,917,053 B2
Combined SHA2 and SHA3 based XMSS hardware accelerator
Santosh Ghosh, Hillsboro, OR (US); Vikram Suresh, Portland, OR (US); Sanu Mathew, Portland, OR (US); Manoj Sastry, Portland, OR (US); Andrew H. Reinders, Portland, OR (US); Raghavan Kumar, Hillsboro, OR (US); and Rafael Misoczki, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 29, 2022, as Appl. No. 17/707,629.
Application 17/707,629 is a continuation of application No. 16/455,950, filed on Jun. 28, 2019, granted, now 11,303,429.
Prior Publication US 2022/0224514 A1, Jul. 14, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 9/06 (2006.01); G06F 7/503 (2006.01); G06F 9/30 (2018.01); H04L 9/32 (2006.01)
CPC H04L 9/0643 (2013.01) [G06F 7/503 (2013.01); G06F 9/3012 (2013.01); H04L 9/3247 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a secure hash algorithm-2 (SHA2) accelerator;
a secure hash algorithm-3 (SHA3) accelerator configurable to perform at least one of a SHAKE-128 function or to perform a SHAKE-256 operation and comprising:
a bit state register to receive a first set of inputs for a plurality of chain functions, a second set of inputs for hashes involved in an L-Tree computation, and a third set of inputs for a Merkle tree root node computation;
a processor to:
receive a 256 bit message input;
perform a set of 24 SHA3 rounds; and
generate a 128 bit output; and
a register bank shared between the SHA2 accelerator and the SHA3 accelerator.