US 11,916,707 B2
Power efficiency in an analog feedback class D modulator
Abhishek Bandyopadhyay, Winchester, MA (US); and Atsushi Matamura, Tokyo (JP)
Assigned to Analog Devices International Unlimited Company, Limerick (IE)
Filed by Analog Devices International Unlimited Company, Limerick (IE)
Filed on Mar. 23, 2022, as Appl. No. 17/701,928.
Application 17/701,928 is a continuation of application No. PCT/EP2020/076655, filed on Sep. 24, 2020.
Claims priority of provisional application 62/905,310, filed on Sep. 24, 2019.
Prior Publication US 2022/0217026 A1, Jul. 7, 2022
Int. Cl. H04L 27/04 (2006.01); H03M 3/00 (2006.01); H04L 27/01 (2006.01)
CPC H04L 27/04 (2013.01) [H03M 3/50 (2013.01); H04L 27/01 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An architecture for a class D modulator, comprising:
a digital input line configured to receive a digital input signal, wherein the digital input line is split into a first parallel line and a second parallel line;
a digital-to-analog converter coupled to the first parallel line, the digital-to-analog converter configured to receive the digital input signal and convert the digital input signal to an analog input signal;
an analog summer configured to subtract an analog feedback signal from the analog input signal and generate an analog summer output;
a loop filter configured to receive the analog summer output and produce a filtered analog output;
a quantizer configured to quantize the filtered analog output and output a quantized signal;
a filter module coupled to the second parallel line configured to digitally filter the digital input signal generating a filtered digital input signal, wherein the filtered digital input signal is fed forward; and
a digital summer configured to add the filtered digital input signal to the quantized signal generating a digital modulator output signal.