US 11,916,703 B2
Error sampler circuit
Abishek Manian, San Jose, CA (US); Nithin Sathisan Poduval, Sunnyvale, CA (US); and Roland Nii Ofei Ribeiro, San Jose, CA (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Dec. 14, 2022, as Appl. No. 18/066,027.
Application 18/066,027 is a division of application No. 17/193,067, filed on Mar. 5, 2021, granted, now 11,575,546.
Prior Publication US 2023/0122240 A1, Apr. 20, 2023
Int. Cl. H04L 25/03 (2006.01); H03K 3/037 (2006.01)
CPC H04L 25/03057 (2013.01) [H03K 3/0372 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An equalizer circuit, comprising:
a decision feedback equalizer (DFE) circuit having a first output and a second output;
a sign-sign least mean squares (SS-LMS) adaptation circuit having a weight value output coupled to the DFE circuit;
an error sampler circuit coupled to the DFE circuit and the SS-LMS adaptation circuit, the error sampler circuit comprising a master latch circuit, and the master latch circuit including a slicer circuit configured to:
generate a first difference signal as a difference of the first output and a first reference signal; and
generate a second difference signal as a difference of the second output and a second reference signal; and
a slave latch circuit coupled to the master latch circuit and the SS-LMS adaptation circuit, and configured to:
generate a third difference signal as a difference of the first difference signal and the second difference signal;
latch the third difference signal; and
provide the third difference signal to the SS-LMS adaptation circuit.