CPC H04B 7/0404 (2013.01) [H04B 7/0413 (2013.01); H04B 7/0417 (2013.01); H04B 7/0695 (2013.01); H04B 7/088 (2013.01); H04L 5/0023 (2013.01); H04L 5/0053 (2013.01); H04W 16/28 (2013.01)] | 22 Claims |
1. An apparatus comprising:
at least one processor; and
at least one non-transitory memory storing instructions that, when executed by the at least one processor, cause the apparatus at least to:
in response to receiving downlink triggering signaling from a base station, transmit uplink signaling with a set of at least one uplink resource indicated by triggering bits of the downlink triggering signaling, wherein the triggering bits of the downlink triggering signaling comprise two bits, and wherein a value of the triggering bits being different from zero indicates to the apparatus to transmit the uplink signaling with the set of at least one uplink resource defined with the value of the triggering bits, and the value of the triggering bits being zero indicates to the apparatus to not transmit the uplink signaling with the set of at least one uplink resource;
receive a reply to the uplink signaling, wherein the reply identifies one or more of the at least one uplink resource; and
send uplink data on the identified one or more of the at least one uplink resource.
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