US 11,916,580 B2
On-chip network analyzer
Jeremy Goldblatt, Encinitas, CA (US); and Chinmaya Mishra, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 23, 2021, as Appl. No. 17/448,543.
Prior Publication US 2023/0106620 A1, Apr. 6, 2023
Int. Cl. H04B 1/04 (2006.01); G01R 27/16 (2006.01); H01P 5/18 (2006.01); H03F 1/32 (2006.01); H03F 3/24 (2006.01)
CPC H04B 1/0475 (2013.01) [G01R 27/16 (2013.01); H01P 5/18 (2013.01); H03F 1/3241 (2013.01); H03F 3/245 (2013.01); H03F 2200/451 (2013.01); H04B 2001/0425 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A circuit, comprising:
a directional coupler having an input port, a through port, a coupled port, and an isolation port;
a first power amplifier coupled to the input port of the directional coupler;
a power detector configured to measure output levels from the coupled port and the isolation port of the directional coupler;
a reference signal generator coupled to the isolation port of the directional coupler;
a vector modulator configured to adjust a phase of a signal generated from the first power amplifier; and
a second power amplifier, wherein the reference signal generator is coupled to the isolation port of the directional coupler through the vector modulator and the second power amplifier.