| CPC H03M 13/458 (2013.01) [H03M 13/1105 (2013.01); H03M 13/256 (2013.01); H03M 13/3715 (2013.01); H03M 13/6331 (2013.01)] | 40 Claims |
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1. A receiver circuit comprising:
a first detector configured i) to detect presence of errors among codeword bits that are recovered from a set of decisions, the set of decisions constituting estimates of bit values transmitted to the receiver circuit, and ii) prior to performing a process to detect bit error sequences in the set of decisions, to generate an enable signal indicative of whether errors have been detected among the recovered codeword bits, without identifying or correcting decisions of the set of decisions that are in error; and
an error correction circuit configured to receive the set of decisions, and in response to the enable signal: i) to perform the process to detect the bit error sequences in the set of decisions; each of the bit error sequences being defined by respective predetermined patterns of error bits; ii) to determine for each one of the detected bit error sequences a likelihood the one of the detected bit error sequences occurring; iii) to select one or more of the detected bit error sequences most likely to include an actual error; and iv) to correct the errors in the recovered codeword bits among the one or more detected bit error sequences selected as most likely to include the actual error.
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