US 11,916,558 B1
DDR phy parallel clock paths architecture
Yong Xu, San Diego, CA (US); Boris Dimitrov Andreev, San Diego, CA (US); Vikas Mahendiyan, San Diego, CA (US); Yuxin Li, San Diego, CA (US); Anand Meruva, San Diego, CA (US); and Jeffrey Mark Hinrichs, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Dec. 13, 2022, as Appl. No. 18/080,728.
Int. Cl. H03L 7/00 (2006.01); G06F 1/12 (2006.01); H03K 19/20 (2006.01); H03L 7/081 (2006.01)
CPC H03L 7/0812 (2013.01) [G06F 1/12 (2013.01); H03K 19/20 (2013.01)] 29 Claims
OG exemplary drawing
 
1. A system, comprising:
a first clock path;
a second clock path;
a delay circuit;
a first multiplexer having a first input, a second input, and an output, wherein the first input of the first multiplexer is coupled to the first clock path, the second input of the first multiplexer is coupled to the second clock path, and the output of the first multiplexer is coupled to the delay circuit;
a first delay control circuit having an input and an output, wherein the input of the first delay control circuit is coupled to the first clock path;
a second delay control circuit having an input and an output, wherein the input of the second delay control circuit is coupled to the second clock path; and
a second multiplexer having a first input, a second input, and an output, wherein the first input of the second multiplexer is coupled to the output of the first delay control circuit, the second input of the second multiplexer is coupled to the output of the second delay control circuit, and the output of the second multiplexer is coupled to a control input of the delay circuit.