US 11,916,554 B2
Techniques for duty cycle correction
Christopher P. Mozak, Portland, OR (US); Ralph S. Li, Portland, OR (US); Chin Wah Lim, Bayan Lepas (MY); Mahmoud Elassal, King City, OR (US); Anant Balakrishnan, Hillsboro, OR (US); and Isaac Ali, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 16, 2019, as Appl. No. 16/716,234.
Prior Publication US 2020/0119721 A1, Apr. 16, 2020
Int. Cl. H03K 3/00 (2006.01); G06F 11/16 (2006.01); H03K 3/017 (2006.01); H03K 5/135 (2006.01); H03K 5/156 (2006.01); H03L 7/081 (2006.01)
CPC H03K 3/017 (2013.01) [G06F 11/1679 (2013.01); H03K 5/135 (2013.01); H03K 5/1565 (2013.01); H03L 7/0816 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a sample clock to measure a duty cycle by periodic sampling of a target clock signal based on a greater than 1 prime number ratio of a reference clock cycle time, wherein the reference clock cycle time is used to set a measurement cycle time over which the duty cycle is to be measured; and
duty cycle correction logic to:
determine a duty cycle error as compared to a programmable target duty cycle based on a measured duty cycle during the measurement cycle time; and
adjust the duty cycle generated by the target clock signal based, at least in part, on the duty cycle error.