| CPC H03K 19/20 (2013.01) [G06F 15/76 (2013.01); G06F 15/82 (2013.01); G06F 18/00 (2023.01); G06N 20/00 (2019.01); H03K 5/22 (2013.01); H04N 1/00336 (2013.01)] | 20 Claims |
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1. An integrated circuit comprising:
a feature extraction pipeline including a plurality of pipeline stages, wherein:
each pipeline stage of the plurality of pipeline stages has a respective plurality of setting bits and a respective accumulator;
each pipeline stage of the plurality of pipeline stages is configured to:
receive a plurality of input symbols;
for each input symbol of the plurality of input symbols, determine whether the input symbol satisfies a condition encoded in the plurality of setting bits; and
when the input symbol satisfies the condition, increment an accumulator value of the accumulator;
the condition encoded in the plurality of setting bits of a dependent pipeline stage of the plurality of pipeline stages includes a conditional dependency on whether a respective prior condition of a prior pipeline stage is satisfied; and
the feature extraction pipeline is configured to output the plurality of accumulator values of the plurality of accumulators included in the pipeline stages.
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