US 11,916,552 B2
Method for supporting multiple concurrent plugins in a programmable integrated circuit
Ellery Cochell, Denver, CO (US); Ripduman Singh Sohan, San Jose, CA (US); and Kieran Mansley, Cambridge (GB)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Mar. 9, 2022, as Appl. No. 17/690,845.
Prior Publication US 2023/0291406 A1, Sep. 14, 2023
Int. Cl. H03K 19/1776 (2020.01); H03K 19/17756 (2020.01); G06F 30/34 (2020.01); H03K 19/00 (2006.01)
CPC H03K 19/1776 (2013.01) [G06F 30/34 (2020.01); H03K 19/17756 (2013.01); H03K 19/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A programmable integrated circuit (IC) comprising:
a static region of programmable circuitry; and
a dynamic region of programmable circuitry, the dynamic region comprising a plurality of partial reconfiguration (PR) regions, each PR region being capable of supporting one or more user-specified circuits, wherein the programmable IC is configured to:
send a first message to a host, indicating that a modification of at least a first user-specified circuit in a first PR region of the plurality of PR regions will occur;
cause a memory to clear and release one or more memory resources related to the first user-specified circuit and to effectively ignore requests from the first PR region, while allowing at least one of:
other memory resources related to other user-specified circuits to operate; or
accesses to the memory from other PR regions; and
modify the at least the first user-specified circuit in the first PR region.