US 11,916,551 B2
Process of routing tile-to-tile interconnects of an FPGA, and method of manufacturing an FPGA
Yongning Liu, San Ramon, CA (US); Fan Mo, San Jose, CA (US); and Cheng C. Wang, San Jose, CA (US)
Assigned to Flex Logix Technologies, Inc., Mountain View, CA (US)
Filed by Flex Logix Technologies, Inc., Mountain View, CA (US)
Filed on Feb. 19, 2022, as Appl. No. 17/676,123.
Application 17/676,123 is a division of application No. 17/106,124, filed on Nov. 29, 2020, granted, now 11,277,135.
Application 17/106,124 is a division of application No. 16/579,766, filed on Sep. 23, 2019, granted, now 10,855,284, issued on Dec. 1, 2020.
Claims priority of provisional application 62/735,988, filed on Sep. 25, 2018.
Prior Publication US 2022/0173738 A1, Jun. 2, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 19/17736 (2020.01); H03K 19/17796 (2020.01); H03K 19/17732 (2020.01)
CPC H03K 19/17744 (2013.01) [H03K 19/17732 (2013.01); H03K 19/17796 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of routing interconnects of an integrated circuit comprising a field programmable gate array including: (i) a plurality of logic tiles, wherein each logic tile includes a logic tile interconnect network having a plurality of switches and a plurality of logic tile interconnects, (ii) a tile-to-tile interconnect network, having a plurality of tile-to-tile interconnects, each having start/end points, to interconnect logic tile networks of the plurality of logic tiles, the method comprising:
routing a first plurality of tile-to-tile interconnects in a first plurality of logic tiles wherein: (i) the first plurality of logic tiles are a first subset of the plurality of logic tiles and (ii) the start/end point of each tile-to-tile interconnect in the first plurality of logic tiles is independent of the start/end point of the other tile-to-tile interconnects in the first plurality of logic tiles;
after routing the first plurality of tile-to-tile interconnects, routing a second plurality of tile-to-tile interconnects in a second plurality of logic tiles wherein: (i) the second plurality of logic tiles are a second subset of the plurality of logic tiles and (ii) the start/end point of each tile-to-tile interconnect in the second plurality of logic tiles is independent of the start/end point of the other tile-to-tile interconnects in the second plurality of logic tiles; and
wherein routing the second plurality of tile-to-tile interconnects in the second plurality of logic tiles includes connecting at least one start/end point of each tile-to-tile interconnect in the second plurality of logic tiles to at least one start/end point of each tile-to-tile interconnect in the first plurality of logic tiles that was routed in the first plurality of logic tiles.