US 11,916,470 B2
Gate driving technique to lower switch on-resistance in switching converter applications
Taewoo Kwak, San Diego, CA (US); Joseph Dale Rutkowski, Chandler, AZ (US); and Sugato Mukherjee, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jun. 16, 2021, as Appl. No. 17/349,687.
Claims priority of provisional application 63/085,341, filed on Sep. 30, 2020.
Prior Publication US 2022/0103073 A1, Mar. 31, 2022
Int. Cl. H02M 1/08 (2006.01)
CPC H02M 1/08 (2013.01) 6 Claims
OG exemplary drawing
 
1. A power supply circuit comprising:
a switching converter having a switching transistor having a source coupled to a first voltage rail; and
a gate driver having an output coupled to a gate of the switching transistor, the gate driver comprising:
a first switching device coupled between the output of the gate driver and the first voltage rail;
a second switching device coupled between the output of the gate driver and a voltage node of the gate driver;
a third switching device coupled between the voltage node of the gate driver and a second voltage rail; and
a voltage clamp coupled in series with a fourth switching device, the voltage clamp and the fourth switching device being coupled between a third voltage rail and the voltage node, wherein:
the switching transistor is a p-type transistor;
the first voltage rail has a first voltage;
the second voltage rail has a second voltage lower than the first voltage; and
the third voltage rail has a third voltage lower than the second voltage.