US 11,916,432 B2
Chip with power-glitch detection
Pin-Wen Chen, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsinchu (TW)
Filed on Sep. 26, 2022, as Appl. No. 17/935,245.
Claims priority of provisional application 63/296,502, filed on Jan. 5, 2022.
Prior Publication US 2023/0216333 A1, Jul. 6, 2023
Int. Cl. G06F 1/26 (2006.01); G01R 19/00 (2006.01); G06F 1/28 (2006.01); G06F 1/30 (2006.01); H02J 9/06 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01)
CPC H02J 9/061 (2013.01) [G01R 19/0084 (2013.01); G06F 1/28 (2013.01); G06F 1/30 (2013.01); H03K 3/037 (2013.01); H03K 19/20 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A chip with power-glitch detection, comprising:
a power terminal, receiving power;
a first inverter having an input terminal coupled to the power terminal; and
a back-up power storage device coupled to the power terminal, transforming the power to back-up power, wherein the first inverter is powered by the back-up power when a power glitch occurs on the power terminal, and the power glitch is reflected at an output terminal of the first inverter;
a latch for presenting a detection result indicating the power glitch, having a positive output terminal that is at a low level before the power glitch, and a negative output terminal that is at a high level before the glitch; and
a switch, closed when the power glitch is reflected at the output terminal of the first inverter, to connect the negative output terminal of the latch to the positive output terminal of the latch;
wherein the latch further has a first capacitor coupling the positive output terminal to the power terminal to pull up a voltage level of the positive output terminal after the power glitch, and the latch further has a second capacitor coupling the negative output terminal to a ground terminal.