US 11,916,376 B2
Overdrive electrostatic discharge clamp
Jie-Ting Chen, Hsinchu (TW); and Wei-Lun Sun, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsinchu (TW)
Filed on Jan. 21, 2022, as Appl. No. 17/580,926.
Claims priority of provisional application 63/181,397, filed on Apr. 29, 2021.
Prior Publication US 2022/0352711 A1, Nov. 3, 2022
Int. Cl. H02H 9/04 (2006.01); H01L 27/02 (2006.01)
CPC H02H 9/046 (2013.01) [H01L 27/0285 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An electrostatic discharge clamp, comprising:
a clamping circuit, comprising a plurality of transistors connected in a cascode configuration between a power line and a system ground, wherein the number of the plurality of transistors depending on an overdriving level on the power line and manufacturing process is greater than two, the overdriving level is 2.5V or 3.3V, and the manufacture process is 5 nm, or 4 nm, or 3 nm or below;
a driving circuit, coupled to gates of the transistors of the clamping circuit;
a capacitor and resistor network, introducing an RC delay in response to an electrostatic discharge event to control the driving circuit to turn on the transistors of the clamping circuit for electrostatic discharging; and
a bias circuit, biasing the driving circuit to turn off the transistors of the clamping circuit when the capacitor and resistor network does not detect the electrostatic discharge event.