US 11,916,165 B2
High voltage monolithic LED chip
Kevin W. Haberern, Cary, NC (US); Matthew Donofrio, Raleigh, NC (US); Bennett Langsdorf, Cary, NC (US); Thomas Place, Franklinton, NC (US); and Michael John Bergmann, Raleigh, NC (US)
Assigned to CreeLED, Inc., Durham, NC (US)
Filed by CREELED, INC., Durham, NC (US)
Filed on Oct. 2, 2020, as Appl. No. 17/062,119.
Application 17/062,119 is a division of application No. 16/173,617, filed on Oct. 29, 2018, granted, now 10,797,201.
Application 16/173,617 is a continuation of application No. 15/647,823, filed on Jul. 12, 2017, granted, now 10,115,860, issued on Oct. 30, 2018.
Application 15/647,823 is a continuation of application No. 14/050,001, filed on Oct. 9, 2013, granted, now 9,728,676, issued on Aug. 8, 2017.
Application 14/050,001 is a continuation in part of application No. 13/168,689, filed on Jun. 24, 2011, granted, now 8,686,429, issued on Apr. 1, 2014.
Prior Publication US 2021/0020805 A1, Jan. 21, 2021
Int. Cl. H01L 33/08 (2010.01); H01L 33/40 (2010.01); H01L 25/075 (2006.01); H01L 33/46 (2010.01)
CPC H01L 33/08 (2013.01) [H01L 25/0753 (2013.01); H01L 33/405 (2013.01); H01L 33/46 (2013.01); H01L 2224/32257 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73265 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A method for fabricating a lighting device, the method comprising:
separating a plurality of LED active regions of a wafer, wherein LED active regions of the plurality of LED active regions are supported by a structure including one or more insulating material layers, including electrically conductive interconnect elements embedded within said one or more insulating material layers, and a plurality of electrically conductive vias extending from the electrically conductive interconnect elements to contact the plurality of LED active regions, wherein the electrically conductive interconnect elements and the plurality of electrically conductive vias connect at least some LED active regions of the plurality of LED active regions in series, in parallel, or in series-parallel; and
mounting the structure to a submount, with the one or more insulating material layers arranged between the submount and the plurality of LED active regions;
wherein the plurality of electrically conductive vias includes a first group of one or more electrically conductive vias coupled with an n-type layer of the plurality of LED active regions, and a second group of one or more electrically conductive vias coupled with a p-type layer of the plurality of LED active regions; and
wherein each electrically conductive via of the first group of one or more electrically conductive vias comprises a greater height than each electrically conductive via of the second group of one or more electrically conductive vias.