US 11,916,122 B2
Gate all around transistor with dual inner spacers
Zhi-Chang Lin, Hsinchu (TW); Kuan-Ting Pan, Hsinchu (TW); Shih-Cheng Chen, Hsinchu (TW); Jung-Hung Chang, Hsinchu (TW); Lo-Heng Chang, Hsinchu (TW); Chien-Ning Yao, Hsinchu (TW); and Kuo-Cheng Chiang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 8, 2021, as Appl. No. 17/370,833.
Prior Publication US 2023/0012216 A1, Jan. 12, 2023
Int. Cl. H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01)
CPC H01L 29/42392 (2013.01) [H01L 29/0665 (2013.01); H01L 29/401 (2013.01); H01L 29/6653 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a stack of semiconductor nanosheets corresponding to channel regions of a gate all around transistor;
forming a plurality of sacrificial semiconductor nanosheets between the semiconductor nanosheets and having a first composition;
forming a sacrificial semiconductor cladding in contact with the stack of semiconductor nanosheets and the sacrificial semiconductor nanosheets and having a second composition different than the first composition;
exposing a portion of the semiconductor nanosheets by recessing the sacrificial semiconductor cladding with a first etching process;
forming a cladding inner spacer on the portion of the semiconductor nanosheets exposed by recessing the sacrificial semiconductor cladding;
removing a portion of each sacrificial semiconductor nanosheet by recessing the sacrificial semiconductor nanosheet with a second etching process; and
forming a respective sheet inner spacer in place of a recessed portion of each sacrificial semiconductor nanosheet.