US 11,916,111 B2
Single crystal semiconductor structure and method of fabricating the same
Junhee Choi, Seongnam-si (KR); Joohun Han, Hwaseong-si (KR); and Vladimir Matias, Santa Fe, NM (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR); and iBeam Materials, Inc., Santa Fe, NM (US)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR); and iBeam Materials, Inc., Santa Fe, NM (US)
Filed on Oct. 19, 2022, as Appl. No. 17/969,420.
Application 17/969,420 is a division of application No. 17/100,340, filed on Nov. 20, 2020, granted, now 11,508,820.
Claims priority of provisional application 62/939,086, filed on Nov. 22, 2019.
Claims priority of application No. 10-2020-0026814 (KR), filed on Mar. 3, 2020.
Prior Publication US 2023/0052686 A1, Feb. 16, 2023
Int. Cl. H01L 21/00 (2006.01); H01L 29/16 (2006.01); H01L 29/04 (2006.01); H01L 21/02 (2006.01)
CPC H01L 29/1604 (2013.01) [H01L 21/0254 (2013.01); H01L 21/0259 (2013.01); H01L 21/02428 (2013.01); H01L 21/02488 (2013.01); H01L 21/02546 (2013.01); H01L 21/02617 (2013.01); H01L 29/04 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A method of fabricating a single crystal semiconductor structure, the method comprising:
forming an orienting thin film on an amorphous substrate;
forming a lower single crystal layer on the orienting thin film;
forming an upper single crystal layer on the lower single crystal layer; and
forming a mask pattern between the lower single crystal layer and the upper single crystal layer,
wherein the orienting thin film has a non-zero thickness that is equal to or less than 10 times a critical thickness hc,
wherein the critical thickness hc is determined by the following equation:

OG Complex Work Unit Math
where b is a Burgers vector of dislocation of the orienting thin film, μ is Poisson's ratio of the orienting thin film, and ε0 is a degree of lattice misfit between the orienting thin film and the lower single crystal layer,
wherein the lower single crystal layer and the upper single crystal layer each comprise a Group III-V compound semiconductor layer,
wherein the mask pattern comprises holes through which the lower single crystal layer is exposed to the upper single crystal layer, and
wherein the upper single crystal layer is formed to fill the holes and cover a top surface of the mask pattern.