US 11,916,106 B2
Source/drain regions in integrated circuit structures
Sean T. Ma, Portland, OR (US); Andy Chih-Hung Wei, Yamhill, OR (US); and Guillaume Bouche, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 11, 2022, as Appl. No. 17/862,094.
Application 17/862,094 is a continuation of application No. 16/829,357, filed on Mar. 25, 2020, granted, now 11,450,736.
Prior Publication US 2022/0344459 A1, Oct. 27, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); H01L 23/00 (2006.01)
CPC H01L 29/0653 (2013.01) [H01L 24/43 (2013.01); H01L 2924/14 (2013.01)] 27 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device, comprising:
a first channel region of a first transistor and an adjacent second channel region of a second transistor;
a first region proximate to the first channel region;
a second region proximate to the second channel region, wherein one of the first region and the second region is one of a source region and a drain region and another one of the first region and the second region is another one of the source region and the drain region; and
an insulating material region at least partially between the first region and the second region, wherein the insulating material region includes a first insulating material and a second insulating material, wherein the first insulating material has a U-shaped cross-section, and the first insulating material is between the second insulating material and the first region.