US 11,916,074 B2
Double rule integrated circuit layouts for a dual transmission gate
Shih-Wei Peng, Hsinchu (TW); Hui-Zhong Zhuang, Kaohsiung (TW); Jiann-Tyng Tzeng, Hsinchu (TW); Li-Chun Tien, Tainan (TW); Pin-Dai Sue, Tainan (TW); and Wei-Cheng Lin, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 27, 2022, as Appl. No. 17/875,060.
Application 16/727,456 is a division of application No. 16/021,847, filed on Jun. 28, 2018, granted, now 10,522,542, issued on Dec. 31, 2019.
Application 17/875,060 is a continuation of application No. 17/120,839, filed on Dec. 14, 2020, granted, now 11,476,250.
Application 17/120,839 is a continuation of application No. 16/727,456, filed on Dec. 26, 2019, granted, now 10,868,008, issued on Dec. 15, 2020.
Prior Publication US 2022/0359512 A1, Nov. 10, 2022
Int. Cl. H01L 21/70 (2006.01); H01L 27/092 (2006.01); H03K 17/687 (2006.01)
CPC H01L 27/092 (2013.01) [H03K 17/6872 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A dual transmission gate, comprising:
a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors that is arranged to form a first transmission gate, the first transmission gate being configured to route a first signal between a first terminal and a second terminal in response to a first clocking signal being at a first logical level and a second clocking signal being at a second logical level, the first pair of CMOS transistors including a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor that is situated along a first column or a second column from among a plurality of columns of an electronic device design real estate and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor that is situated along the first column or the second column;
a second pair of CMOS transistors that is arranged to form a second transmission gate, the second transmission gate being configured to route a second signal between the second terminal and a third terminal in response to the first clocking signal being at the second logical level and the second clocking signal being at the first logical level, the second pair of CMOS transistors including a second PMOS transistor that is situated along the first column or the second column and a second NMOS transistor that is situated along the first column or the second column;
a first region, corresponding to the first clocking signal, situated along a first interconnection layer of a semiconductor stack along a first row from among a plurality of rows of the electronic device design real estate, the first region being connected to the first PMOS transistor and the second NMOS transistor;
a second region, corresponding to the first terminal, situated along the first interconnection layer along a second row from among the plurality of rows of the electronic device design real estate and connected to the first PMOS transistor and the first NMOS transistor;
a third region, corresponding to the second terminal, situated along a second interconnection layer of the semiconductor stack along a second column from among the plurality of columns and connected to the first pair of CMOS transistors and the second pair of CMOS transistors;
a fourth region, corresponding to the second clocking signal, situated along the first interconnection layer along a third row from among the plurality of rows of the electronic device design real estate and connected to the first NMOS transistor and the second PMOS transistor; and
a fifth region, corresponding to the third terminal, situated along the first interconnection layer along a fourth row from among the plurality of rows of the electronic device design real estate and connected to the second PMOS transistor and the second NMOS transistor.