US 11,916,073 B2
Stacked complementary field effect transistors
Ruilong Xie, Niskayuna, NY (US); Kangguo Cheng, Schenectady, NY (US); Julien Frougier, Albany, NY (US); and Chanro Park, Clifton Park, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Aug. 3, 2021, as Appl. No. 17/392,691.
Prior Publication US 2023/0040712 A1, Feb. 9, 2023
Int. Cl. H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 21/822 (2006.01); H01L 29/786 (2006.01); H01L 21/8238 (2006.01); H01L 29/417 (2006.01); H01L 29/06 (2006.01); H01L 27/06 (2006.01); H01L 29/775 (2006.01)
CPC H01L 27/092 (2013.01) [H01L 21/8221 (2013.01); H01L 21/823814 (2013.01); H01L 27/0688 (2013.01); H01L 29/0665 (2013.01); H01L 29/41725 (2013.01); H01L 29/42392 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A complementary field effect transistor (CFET) structure comprising:
a first transistor disposed above a second transistor;
a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, wherein the first source/drain region comprises a smaller cross-section than the second source/drain region;
a first dielectric material disposed in contact with a bottom surface and vertical surfaces of the first source/drain and further in contact with a vertical surface and top surface of the second source/drain region;
a second dielectric material disposed as an interlayer dielectric material encapsulating the first transistor and the second transistor;
a third source/drain region of the first transistor disposed above a fourth source/drain region of the second transistor; and
a first metal contact disposed around and in contact with each of the third source/drain region and fourth source/drain region.