US 11,916,064 B2
Integrated circuit with fault reporting structure
Chiahsin Chang, Cupertino, CA (US); Tao Zhao, San Jose, CA (US); and Xintong Lyu, San Jose, CA (US)
Assigned to Monolithic Power Systems, Inc., San Jose, CA (US)
Filed by Monolithic Power Systems, Inc., San Jose, CA (US)
Filed on Sep. 28, 2021, as Appl. No. 17/487,162.
Prior Publication US 2023/0099928 A1, Mar. 30, 2023
Int. Cl. H01L 27/02 (2006.01); H01L 23/525 (2006.01)
CPC H01L 27/0292 (2013.01) [H01L 23/525 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A fault reporting structure of an integrated circuit having at least one power MOSFET, wherein the at least one power MOSFET has a plurality of MOSFET cells with each MOSFET cell having a drain metal and a source metal, wherein the integrated circuit has a power MOSFET area for routing the drain metals and the source metals of the plurality of MOSFET cells, the fault reporting structure comprising:
a metal net routed in the power MOSFET area or in an area above or below the power MOSFET area; and
a fault reporting pin coupled to the metal net and configured to provide a fault signal indicating whether the integrated circuit is in a normal status or in a fault status.