US 11,915,997 B2
Thermal management of GPU-HBM package by microchannel integrated substrate
Xiaopeng Qu, Boise, ID (US); Hyunsuk Chun, Boise, ID (US); and Eiichi Nakano, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 11, 2020, as Appl. No. 16/990,943.
Claims priority of provisional application 63/043,718, filed on Jun. 24, 2020.
Prior Publication US 2021/0407889 A1, Dec. 30, 2021
Int. Cl. H01L 23/473 (2006.01); H01L 25/065 (2023.01); H01L 25/00 (2006.01); H01L 23/367 (2006.01); H01L 21/48 (2006.01); H01L 25/18 (2023.01)
CPC H01L 23/4735 (2013.01) [H01L 21/4871 (2013.01); H01L 23/3672 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor assembly, comprising:
a substrate including
a mounting portion including mounting sites,
contacts corresponding to the mounting sites,
a base portion including terminals electrically coupled to the contacts, and
a core region between the mounting portion and the base portion, the core region including a slot or a groove;
a microchannel module inserted in the slot or the groove and including a microchannel, wherein the microchannel includes a first duct and a second duct spaced apart from the first duct by a common thermally conductive wall, wherein the first duct and the second duct extend in at least approximately the same direction, and wherein a first portion of a flow through the first duct has an approximately opposite direction to a second portion of the flow through the second duct;
a logic device mounted over the microchannel module on a central portion of the substrate and electrically coupled to the contacts of the substrate, wherein the microchannel is configured to remove thermal energy from a bottom portion of the logic device; and
a memory device mounted over the microchannel module on a peripheral portion of the substrate, wherein the microchannel is configured to remove thermal energy from a bottom portion of the memory device,
wherein (a) the memory device is positioned adjacent to an inlet of the microchannel and the logic device is positioned adjacent to an outlet of the microchannel, or (b) the memory device is positioned adjacent to the outlet of the microchannel and the logic device is positioned adjacent to the inlet of the microchannel.