US 11,915,969 B2
Semiconductor structure and manufacturing method thereof
Chen-Chiang Liu, Hsinchu County (TW); and Hung-Kwei Liao, Taoyuan (TW)
Assigned to Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed by Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed on Mar. 6, 2022, as Appl. No. 17/687,663.
Claims priority of application No. 111102699 (TW), filed on Jan. 21, 2022.
Prior Publication US 2023/0238270 A1, Jul. 27, 2023
Int. Cl. H01L 21/762 (2006.01); H01L 23/373 (2006.01); H01L 27/082 (2006.01); H01L 21/763 (2006.01); H01L 27/12 (2006.01)
CPC H01L 21/76224 (2013.01) [H01L 23/3736 (2013.01); H01L 21/763 (2013.01); H01L 27/082 (2013.01); H01L 27/1203 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a substrate;
a deep trench isolation structure disposed in the substrate and not electrically connected to any device, wherein the deep trench isolation structure comprises:
a heat dissipation layer disposed in the substrate; and
a dielectric liner layer disposed between the heat dissipation layer and the substrate;
a heat sink disposed on the heat dissipation layer; and
an interconnect structure disposed between the heat sink and the heat dissipation layer, wherein the interconnect structure is in direct and physical contact with the heat sink and the heat dissipation layer.