US 11,915,966 B2
Backside power rail integration
Ruilong Xie, Niskayuna, NY (US); Takeshi Nogami, Schenectady, NY (US); Roy R. Yu, Poughkeepsie, NY (US); Balasubramanian Pranatharthiharan, Watervliet, NY (US); Albert M. Young, Fishkill, NY (US); Kisik Choi, Watervliet, NY (US); and Brent Anderson, Jericho, VT (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Jun. 9, 2021, as Appl. No. 17/342,650.
Prior Publication US 2022/0399224 A1, Dec. 15, 2022
Int. Cl. H01L 21/74 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 27/088 (2006.01)
CPC H01L 21/743 (2013.01) [H01L 21/76805 (2013.01); H01L 23/5286 (2013.01); H01L 23/535 (2013.01); H01L 27/0886 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first substrate;
a second substrate;
a SiGe layer provided between the first substrate and the second substrate;
a buried power rail (BPR) extending through the first substrate and the SiGe layer, a bottom portion of the BPR having portions extending laterally therefrom in the SiGe layer and having a width greater than a width of a top portion of the BPR; and
a nano though-silicon via formed in the second substrate in contact with the BPR,
wherein a width of the bottom portion of the BPR is greater than a width of the nano through-silicon via in contact therewith, and
wherein a thickness of the bottom portion of the BPR is less than a width of the top portion of the BPR.