CPC H01J 37/32146 (2013.01) [H01J 37/321 (2013.01); H01J 37/32183 (2013.01); H01J 37/32568 (2013.01); H01L 21/6833 (2013.01); H01J 2237/334 (2013.01); H01L 21/3065 (2013.01); H01L 21/67069 (2013.01)] | 20 Claims |
1. A controller comprising:
a processor configured to:
control a primary radio frequency (RF) generator to output a primary RF signal that pulses in a first manner between a primary frequency level during a first time period and an off frequency level during a second time period;
control a secondary RF generator to output a secondary RF signal that pulses in a second manner between the off frequency level during the first time period and a secondary frequency level during the second time period, wherein the primary and secondary RF generators are coupled to an upper electrode of a plasma chamber via an impedance matching network;
control the primary RF generator to output the primary RF signal that pulses between the primary and off frequency levels during additional time periods in the same first manner as that during the first and second time periods; and
control the secondary RF generator to output the secondary RF signal that pulses between the off and secondary frequency levels during the additional time periods in the same second manner as that during the first and second time periods; and
a memory device coupled to the processor.
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