CPC G11C 7/08 (2013.01) [G11C 7/065 (2013.01); G11C 7/12 (2013.01); G11C 11/22 (2013.01); G11C 11/221 (2013.01); G11C 11/2273 (2013.01); G11C 7/14 (2013.01); G11C 11/406 (2013.01); G11C 11/4091 (2013.01); G11C 11/4093 (2013.01); G11C 2207/002 (2013.01); G11C 2207/06 (2013.01)] | 14 Claims |
1. An apparatus, comprising:
a memory cell;
an input/output component; and
a sense component comprising:
a first portion configured to couple with the memory cell, the first portion comprising a first plurality of transistors;
a second portion configured to couple with the input/output component, the second portion comprising a second plurality of transistors; and
a third portion coupled with the first portion and the second portion and comprising a third plurality of transistors each having a respective gate that is operable to couple with a voltage source, the third portion configured to:
isolate the second portion from voltages of first signals of the first portion that are greater than a threshold that is associated with a voltage of the voltage source; and
generate second signals of the second portion based at least in part on the first signals of the first portion, the second signals having voltages that are less than the threshold that is associated with the voltage of the voltage source.
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