US 11,915,774 B2
Memory devices and methods for managing error regions
Joe M. Jeddeloh, Shoreview, MN (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 11, 2021, as Appl. No. 17/498,480.
Application 13/405,554 is a division of application No. 12/359,014, filed on Jan. 23, 2009, granted, now 8,127,185.
Application 17/498,480 is a continuation of application No. 16/430,121, filed on Jun. 3, 2019, granted, now 11,145,384.
Application 16/430,121 is a continuation of application No. 15/927,679, filed on Mar. 21, 2018, granted, now 10,347,356.
Application 15/927,679 is a continuation of application No. 14/664,547, filed on Mar. 20, 2015, granted, now 9,953,724.
Application 14/664,547 is a continuation of application No. 13/784,510, filed on Mar. 4, 2013, granted, now 8,990,647.
Application 13/784,510 is a continuation of application No. 13/405,554, filed on Feb. 27, 2012, granted, now 8,392,771.
Prior Publication US 2022/0027236 A1, Jan. 27, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/44 (2006.01); G11C 5/04 (2006.01); G11C 29/00 (2006.01); G11C 29/12 (2006.01); H01L 25/18 (2023.01); H01L 27/06 (2006.01); H01L 27/105 (2023.01); H10B 12/00 (2023.01)
CPC G11C 29/44 (2013.01) [G11C 29/4401 (2013.01); G11C 29/76 (2013.01); H01L 25/18 (2013.01); H10B 12/50 (2023.02); G11C 5/04 (2013.01); G11C 2029/1208 (2013.01); H01L 27/0688 (2013.01); H01L 27/105 (2013.01); H01L 2924/0002 (2013.01); Y10T 29/49002 (2015.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a stack of multiple memory die electrically connected with one another by through wafer interconnects extending through the stack of multiple memory die, the stack of multiple memory die comprising multiple partitions respectively including one or more arrays from each of two or more memory die of the stack of multiple memory die, the multiple partitions comprising multiple first partitions established according to a first memory map; and
control logic operably coupled to the stack of multiple memory die, the control logic operable to monitor portions of the stack of multiple memory die to collect error data indicating defective portions within one or more of the multiple partitions, and to remove a defective portion from one or more of the multiple partitions.