US 11,915,772 B1
Data storage device and method for power on reset and read error handling
Vishal Sharma, Bangalore (IN); Darshan Pagariya, Gondia (IN); and Sourabh Sankule, Bangalore (IN)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Sep. 2, 2022, as Appl. No. 17/902,113.
Int. Cl. G11C 29/02 (2006.01); G06F 3/06 (2006.01)
CPC G11C 29/021 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data storage device comprising:
a memory comprising a plurality of memory cells; and
a controller coupled with the memory and configured to:
send a first command to the memory that specifies an initial read voltage threshold and a voltage shift;
send a second command to the memory a plurality of times, wherein the memory is configured to, each time in response to receiving the second command:
(a) read data from the plurality of memory cells using a read voltage threshold;
(b) send the data read from the plurality of memory cells to the controller; and
(c) increment the read voltage threshold by a multiple of the voltage shift;
wherein:
a first time the memory receives the second command, the plurality of memory cells are read using the initial read voltage threshold;
each subsequent time the memory receives the second command, the plurality of memory cells are read using the initial read voltage threshold incremented by a different multiple of the voltage shift; and
the memory incrementing the read voltage threshold in response to receiving the second commands avoids a latency that would be incurred by the controller specifying an incremented read voltage threshold.