US 11,915,764 B2
Apparatus and methods for thermal management in a memory
Jeremy Binfet, Boise, ID (US); and Kishore Kumar Muchherla, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Mar. 25, 2022, as Appl. No. 17/704,154.
Prior Publication US 2023/0326527 A1, Oct. 12, 2023
Int. Cl. G11C 5/06 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 5/063 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An memory, comprising:
an array of memory cells; and
a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
initiate an array operation;
indicate an unavailability to initiate a next array operation;
append a delay interval to an array access time of the array operation, wherein the delay interval has a duration determined in response to an indication of temperature; and
indicate an availability to initiate a next array operation in response to a completion of the delay interval.