US 11,915,741 B2
Apparatuses and methods for logic/memory devices
Richard C. Murphy, Boise, ID (US)
Filed by Lodestar Licensing Group LLC, Evanston, IL (US)
Filed on Feb. 3, 2023, as Appl. No. 18/105,442.
Application 16/004,864 is a division of application No. 15/066,831, filed on Mar. 10, 2016, granted, now 9,997,232, issued on Jun. 12, 2018.
Application 18/105,442 is a continuation of application No. 17/157,447, filed on Jan. 25, 2021, granted, now 11,594,274.
Application 17/157,447 is a continuation of application No. 16/440,477, filed on Jun. 13, 2019, granted, now 10,902,906, issued on Jan. 26, 2021.
Application 16/440,477 is a continuation of application No. 16/004,864, filed on Jun. 11, 2018, granted, now 10,559,347, issued on Feb. 11, 2020.
Prior Publication US 2023/0186975 A1, Jun. 15, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/10 (2006.01); G11C 11/4091 (2006.01); G11C 11/4076 (2006.01); G11C 7/08 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); G06F 3/06 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 7/08 (2013.01); G11C 7/1006 (2013.01); G11C 11/4076 (2013.01); G06F 3/068 (2013.01); G06F 3/0611 (2013.01); G06F 3/0659 (2013.01); G11C 7/1048 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a plurality of processing in memory (PIM) devices to perform PIM operations, the plurality of PIM devices comprising:
a first PIM device comprising:
a first plurality of banks, each bank of the first plurality of banks comprising a respective array of memory cells and respective sensing circuitry, wherein at least two banks of the first plurality of banks are on different memory components of a plurality of memory components stacked with a logic component;
a first plurality of timing circuitries respectively coupled to the first plurality of banks; and
a first control logic on the logic component coupled to the first plurality of banks and the first plurality of timing circuitries; and
a second PIM device comprising:
a second plurality of banks, each bank of the second plurality of banks comprising a respective array of memory cells and respective sensing circuitry, wherein at least two banks of the second plurality of banks are on different memory components of the plurality of memory components;
a second plurality of timing circuitries respectively coupled to the second plurality of banks; and
a second control logic on the logic component coupled to the second plurality of banks and the second plurality of timing circuitries; and
wherein the plurality of PIM devices further comprises switching circuitry configured to:
route memory array requests received from a host; and
route PIM requests received from the host to perform a logical operation.