US 11,915,740 B2
Parallel access in a memory array
Efrem Bolandrina, Fiorano al Serio (IT); Andrea Martinelli, Bergamo (IT); Christophe Vincent Antoine Laurent, Agrate Brianza (IT); and Ferdinando Bedeschi, Biassono (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 3, 2022, as Appl. No. 17/686,240.
Prior Publication US 2023/0282270 A1, Sep. 7, 2023
Int. Cl. G11C 8/00 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4093 (2006.01)
CPC G11C 11/4082 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); G11C 11/4093 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of pillars arranged in a two-dimensional array of a first quantity of pillars along a first direction and a second quantity of pillars along a second direction, each pillar of the plurality of pillars coupled with a respective plurality of memory cells;
a plurality of activation lines each operable to activate a respective set, having the second quantity of pillars, of the plurality of pillars along the second direction;
a plurality of first word lines each coupled with a respective memory cell of each pillar of a first subset of the plurality of pillars, the first subset arranged in a two-dimensional array of the first quantity of pillars along the first direction and a third quantity of pillars along the second direction and less than the second quantity of pillars;
a first word line driver operable to bias one of the plurality of first word lines;
a plurality of second word lines each coupled with a respective memory cell of each pillar of a second subset of the plurality of pillars, the second subset arranged in a two-dimensional array of the first quantity of pillars along the first direction and the third quantity of pillars along the second direction; and
a second word line driver operable to bias one of the plurality of second word lines.