US 11,915,739 B2
On-chip device testing circuit that generates noise on power bus of memory device
Eric A. Becker, Boise, ID (US); and Tyler J. Gomm, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 21, 2021, as Appl. No. 17/558,512.
Prior Publication US 2023/0197138 A1, Jun. 22, 2023
Int. Cl. G11C 5/14 (2006.01); G06F 7/58 (2006.01); G11C 11/401 (2006.01); G11C 11/4074 (2006.01); G11C 11/4076 (2006.01)
CPC G11C 11/4074 (2013.01) [G06F 7/584 (2013.01); G11C 5/14 (2013.01); G11C 5/143 (2013.01); G11C 11/401 (2013.01); G11C 11/4076 (2013.01); G06F 2207/581 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a bus shorting circuit connected between a first rail of a power bus supplying power to a component of a memory device and a second rail of the power bus; and
a pulse generator circuit connected to the bus shorting circuit and configured to intermittently connect the first rail to the second rail to induce noise on the power bus,
wherein the induced noise is based on a noise test profile for the power bus, the noise test profile corresponding to a magnitude limit on a deflection of a voltage amplitude of the power bus.