US 11,915,735 B2
Sensing scheme for a memory with shared sense components
Yuan He, Boise, ID (US); Tae H. Kim, Boise, ID (US); and Scott James Derner, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 21, 2022, as Appl. No. 18/048,738.
Application 18/048,738 is a continuation of application No. 17/171,873, filed on Feb. 9, 2021, granted, now 11,501,815.
Prior Publication US 2023/0148359 A1, May 11, 2023
Int. Cl. G11C 11/22 (2006.01)
CPC G11C 11/2273 (2013.01) [G11C 11/221 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first switching component configured to couple a first digit line of a first memory cell, in a first tier of memory cells, with an input of a sense component;
a second switching component configured to couple a second digit line of a second memory cell, in the first tier of memory cells, with the input of the sense component, the second memory cell coupled with a different word line than the first memory cell and coupled with a different plate line than the first memory cell;
the sense component configured to sense the first memory cell and the second memory cell at different times;
a third switching component, in a second tier of memory cells, configured to couple a third digit line of a third memory cell with a second input of a second sense component; and
a fourth switching component, in the second tier of memory cells, configured to couple a fourth digit line of a fourth memory cell with the second input of the second sense component.