| CPC G06Q 40/04 (2013.01) [H04L 47/193 (2013.01); H04L 47/564 (2013.01)] | 20 Claims |
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1. A system comprising:
at least one first programmable integrated circuit communicatively coupled to a plurality of first transmission control protocol (TCP) client circuits, in which each of the first TCP client circuits is configured to receive order data from a market participant,
in which the at least one first programmable integrated circuit is configured to:
receive, from each of the first TCP client circuits, a stream of data packets representative of at least one order; and
for each order of the at least one order,
identify a last data byte (LDB) data packet in the stream of data packets containing an identifier indicating a LDB of a plurality of data bytes forming the order;
determine a time stamp for the order based on a time indicated by a time stamp clock at a time of receipt of the LDB data packet of the order at the at least one first programmable integrated circuit; and
generate at least one order message for the order, in which the at least one order message indicates the time stamp for the order;
at least one processor configured to:
for each order for which at least one order message is generated:
determine an updated time stamp based on a time offset associated with a given first TCP client circuit of the first TCP client circuits from which the order is received, in which the time offset corresponds to a network path extending from the given first TCP circuit client to the at least one first programmable integrated circuit, and in which each of the first TCP client circuits has a time offset corresponding to a network path extending respectively from the first TCP client circuit to the at least one first programmable integrated circuit; and
generate an updated order message indicating the updated time stamp;
a sequencer of at least one second programmable integrated circuit configured to:
receive a plurality of updated order messages for the respective orders;
assign a sequencer time stamp to each of the respective orders corresponding to a time indicated by a sequencer clock at a time of receipt of the updated order message corresponding to the respective order at the sequencer;
in a first queue, order the respective orders in time sequence, starting with an earliest time, based on the updated time stamps;
in a second queue, order the respective orders in time sequence, starting with an earliest time, based on the sequencer time stamps;
compare a time of the sequencer clock with the sequencer time stamps of the respective orders in the second queue,
when, for a given order in the second queue, the time of the sequencer clock is determined to be same as or after a sum of the sequencer time stamp for the given order and a hold delay:
remove the given order from the second queue;
interleave into an output stream, in time sequence order starting with an earliest time based on a respective updated time stamp, the updated order message of the given order and an updated order message of each other order in the first queue, if any, having an updated time stamp earlier than the updated time stamp of the given order;
remove, from the first queue, the given order and, if in the first queue, the each other order; and
remove, from the second queue, the each other order, if in the second queue; and
a fanout circuit of the at least one second programmable integrated circuit communicatively coupled to a plurality of TCP server circuits, in which the fanout circuit is configured to:
for each order represented in the output stream, instruct at least two of the TCP server circuits to simultaneously transmit a second stream of output data packets representative of the order represented in the output stream.
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