US 11,915,057 B2
Computational partition for a multi-threaded, self-scheduling reconfigurable computing fabric
Tony M. Brewer, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 23, 2023, as Appl. No. 18/100,135.
Application 18/100,135 is a continuation of application No. 16/994,607, filed on Aug. 16, 2020, granted, now 11,573,834.
Claims priority of provisional application 62/890,366, filed on Aug. 22, 2019.
Prior Publication US 2023/0153163 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/50 (2006.01); G06F 13/42 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/505 (2013.01) [G06F 9/3009 (2013.01); G06F 9/30029 (2013.01); G06F 9/3871 (2013.01); G06F 9/5061 (2013.01); G06F 13/4226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first, synchronous network;
a second, packet network;
a plurality of configurable circuits arranged in an array, each configurable circuit of the plurality of configurable circuits coupled to the first, synchronous network and to the second, packet network, each configurable circuit of the plurality of configurable circuits comprising:
a configurable computation circuit; and
a configuration memory coupled to the configurable computation circuit, the configuration memory comprising:
a first instruction memory configured to store a first plurality of configuration instructions to configure the configurable computation circuit; and
a second instruction memory configured to store a second plurality of configuration instructions or instruction indices for selection of a configuration instruction of the first plurality of configuration instructions from the first instruction memory and for selection of a network input from the first network for receipt of the configuration instruction or a configuration instruction index from another configurable circuit of the plurality of configurable circuits of the array;
and
a dispatch interface circuit coupled to the plurality of configurable circuits through the second, packet network, the dispatch interface circuit configured to partition the plurality of configurable circuits of the array into a plurality of partitions of configurable circuits and to load one or more computation kernels into one or more configurable circuits of the plurality of partitions of configurable circuits.