US 11,915,002 B2
Providing extended branch target buffer (BTB) entries for storing trunk branch metadata and leaf branch metadata
Saransh Jain, Raleigh, NC (US); Rami Mohammad Al Sheikh, Morrisville, NC (US); Daren Eugene Streett, Cary, NC (US); and Michael Scott McIlvaine, Raleigh, NC (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Jun. 24, 2022, as Appl. No. 17/808,916.
Prior Publication US 2023/0418615 A1, Dec. 28, 2023
Int. Cl. G06F 9/38 (2018.01)
CPC G06F 9/3806 (2013.01) [G06F 9/3867 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A processor, comprising:
an instruction processing circuit configured to process an instruction stream comprising a plurality of instructions in an instruction pipeline; and
a branch target buffer (BTB) circuit comprising a BTB comprising a plurality of extended BTB entries, wherein each extended BTB entry of the plurality of extended BTB entries comprises a plurality of branch entries each configured to store metadata comprising either trunk branch metadata or leaf branch metadata;
the BTB circuit configured to:
store trunk branch metadata for a first branch instruction among the plurality of instructions in a first branch entry of an extended BTB entry of the plurality of extended BTB entries, wherein the extended BTB entry corresponds to a first aligned memory block containing an address of the first branch instruction;
store leaf branch metadata for a second branch instruction among the plurality of instructions in a second branch entry of the extended BTB entry in association with the trunk branch metadata, wherein an address of the second branch instruction is subsequent to a target address of the first branch instruction within a second aligned memory block; and
update the first branch entry to store an index of the second branch entry as a leaf branch index.