US 11,914,940 B2
System for designing a semiconductor device, device made, and method of using the system
Jaw-Juinn Horng, Hsinchu (TW); Wen-Shen Chou, Hsinchu (TW); and Yung-Chow Peng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Mar. 12, 2021, as Appl. No. 17/200,366.
Application 17/200,366 is a division of application No. 16/022,680, filed on Jun. 28, 2018, granted, now 10,949,598.
Application 16/022,680 is a division of application No. 14/879,692, filed on Oct. 9, 2015, granted, now 10,026,725, issued on Jul. 17, 2018.
Application 14/879,692 is a division of application No. 13/569,717, filed on Aug. 8, 2012, granted, now 9,158,883, issued on Oct. 13, 2015.
Prior Publication US 2021/0200929 A1, Jul. 1, 2021
Int. Cl. G06F 30/398 (2020.01); G06F 30/392 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 30/392 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A system for manufacturing a semiconductor device comprising:
an array edge detection tool configured to determine whether a layout design of the semiconductor device includes a plurality of active cells or at least one dummy cell;
a layout style determination tool configured to detect whether the plurality of active cells have a distributed layout style;
a layout versus schematic (LVS) tool configured to compare a schematic design of the semiconductor device to the layout design of the semiconductor device; and
a dummy insertion tool configured to revise the layout design of the semiconductor device based on the layout design and the schematic design by revising an area of the at least one dummy cell when the array edge detection tool determines that the layout design includes the at least one dummy cell, or inserting the at least one dummy cell between the plurality of active cells and an outside edge of the semiconductor device when the array edge detection tool determines that the layout design does not include the at least one dummy cell.