US 11,914,893 B2
Managed memory systems with multiple priority queues
Nicola Del Gatto, Cassina de' Pecchi (IT); Massimiliano Patriarca, Milan (IT); Antonino Caprì, Bergamo (IT); Emanuele Confalonieri, Segrate (IT); and Angelo Alberto Rovelli, Agrate Brianza (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 18, 2020, as Appl. No. 16/951,985.
Prior Publication US 2022/0155997 A1, May 19, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0635 (2013.01); G06F 3/0656 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of an electronic device, cause the electronic device to:
receive, at an interface, memory access commands from a host;
store the memory access commands in a command queue;
determine a first subset of the memory access commands associated with a first priority and a second subset of the memory access commands associated with a second priority;
route, from the command queue to a first queue, the first subset of the memory access commands associated with the first priority;
route, from the command queue to a second queue, the second subset of the memory access commands associated with the second priority;
store, in a buffer coupled with the interface, data associated with the memory access commands;
transfer, by a processor of the one or more processors, the first subset of the memory access commands from the first queue at a storage controller to a third queue at the storage controller according to a first process, the third queue associated with the first priority;
transfer, by the processor and concurrent with transferring the first subset of the memory access commands from the first queue to the third queue, the second subset of the memory access commands from the second queue at the storage controller to a fourth queue at the storage controller according to a second process, the fourth queue associated with the second priority, wherein processing the first subset of the memory access commands and processing the second subset of the memory access commands are run concurrently by an execution unit of the processor according to a quantity of the memory access commands in the command queue for a prioritization between the first priority and the second priority; and
move, by the storage controller, the data associated with the memory access commands between the buffer and a storage memory comprising a plurality of memory cells.