US 11,914,890 B2
Trim value loading management in a memory sub-system
Steven Michael Kientz, Westminster, CO (US); and Vamsi Pavan Rayaprolu, Santa Clara, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 13, 2023, as Appl. No. 18/168,300.
Application 18/168,300 is a continuation of application No. 17/068,327, filed on Oct. 12, 2020, granted, now 11,604,601.
Prior Publication US 2023/0195366 A1, Jun. 22, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0625 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
in response to a power up of a memory sub-system, executing a first loading process to load a sequence of a set of trim values into one or more registers of the memory sub-system;
in response to a request to execute a memory access operation, interrupting the first loading process;
executing a second loading process comprising loading a portion of the set of trim values corresponding to the request;
executing the memory access operation using the portion of the set of trim values loaded into the one or more registers during the second loading process; and
following execution of the memory access operation, resuming the first loading process to load one or more unloaded trim values of the sequence of trim values.