US 11,914,889 B2
Managing an adjustable write-to-read delay based on cycle counts in a memory sub-system
Murong Lang, San Jose, CA (US); Tingjun Xie, Milpitas, CA (US); Wei Wang, Dublin, CA (US); Frederick Adi, Castro Valley, CA (US); Zhenming Zhou, San Jose, CA (US); and Jiangli Zhu, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 30, 2022, as Appl. No. 18/071,930.
Application 18/071,930 is a continuation of application No. 16/934,406, filed on Jul. 21, 2020, granted, now 11,526,295.
Prior Publication US 2023/0090523 A1, Mar. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
determining a current cycle count associated with a memory sub-system;
measuring a temperature associated with the memory sub-system;
identifying, in a data structure, a current lifecycle stage corresponding to the current cycle count;
in response to identifying the current lifecycle stage, identifying, in the data structure, a threshold range corresponding to the temperature associated with the memory sub-system;
selecting, from the data structure, a write-to-read (W2R) delay time corresponding to the current lifecycle stage and the threshold range associated with the temperature associated with the memory sub-system; and
executing, by a processing device, a read operation associated with a memory unit of the memory sub-system, following a period of at least the W2R delay time from a time of an execution of a write operation associated with the memory unit.