US 11,914,888 B2
Memory component with input/output data rate alignment
Frederick A. Ware, Los Altos Hills, CA (US); John Eric Linstadt, Palo Alto, CA (US); and Torsten Partsch, San Jose, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Jun. 28, 2022, as Appl. No. 17/852,165.
Application 17/852,165 is a continuation of application No. 16/329,051, granted, now 11,403,030, previously published as PCT/US2017/041248, filed on Jul. 7, 2017.
Claims priority of provisional application 62/382,939, filed on Sep. 2, 2016.
Prior Publication US 2023/0009384 A1, Jan. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 13/16 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 11/4076 (2006.01); G11C 11/4096 (2006.01); H01L 25/065 (2023.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06F 13/1668 (2013.01); G11C 7/06 (2013.01); G11C 7/1057 (2013.01); G11C 7/106 (2013.01); G11C 7/1066 (2013.01); G11C 7/1087 (2013.01); G11C 7/1093 (2013.01); G11C 7/22 (2013.01); G11C 11/4076 (2013.01); G11C 11/4096 (2013.01); H01L 25/0657 (2013.01); G06F 2213/16 (2013.01); G11C 7/1015 (2013.01); G11C 2207/107 (2013.01); G11C 2207/2272 (2013.01); G11C 2207/2281 (2013.01); G11C 2207/229 (2013.01); H01L 2225/06541 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A memory component comprising:
a first core storage array to provide successive sets of N data bits over successive core-readout intervals, respectively, N being a nonzero integer; and
output circuitry to receive the successive sets of N data bits from the first core storage array and to output the successive sets of N data bits from the memory component over successive data-output intervals, respectively, each one of the data-output intervals being briefer than any one of the core-readout intervals.