US 11,914,876 B2
Asynchronous power loss handling approach for a memory sub-system
Michael G. Miller, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 4, 2021, as Appl. No. 17/444,416.
Application 17/444,416 is a continuation of application No. 15/929,883, filed on May 27, 2020, granted, now 11,106,372.
Claims priority of provisional application 62/954,235, filed on Dec. 27, 2019.
Prior Publication US 2021/0365184 A1, Nov. 25, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0625 (2013.01); G06F 3/0685 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
detecting an occurrence of an asynchronous power loss (APL) event in the system;
responsive to detecting the occurrence of the APL event, performing an APL handling operation comprising:
identifying a last written page at a first page location in a block of the memory device, wherein the last written page is associated with a memory cell of the memory device;
copying data from the last written page and from a related page associated with the memory cell to a temporary storage area in the memory device, wherein the related page is part of a same page stack associated with a same wordline of the memory device as the last written page;
incrementing a write-pointer associated with the last written page by a deterministic number of pages;
copying the data from the temporary storage area to a second page location in the block of the memory device, wherein the second page location is identified by the write-pointer; and
providing a notification that the memory device has recovered from the APL event.