US 11,914,865 B2
Methods and systems for limiting data traffic while processing computer system operations
Yamin Friedman, Haifa (IL); Idan Burstein, Akko (IL); Hillel Chapman, Ramat Hashofet (IL); and Gal Yefet, Haifa (IL)
Assigned to Mellanox Technologies, Ltd., Yokneam (IL)
Filed by Mellanox Technologies, Ltd., Yokneam (IL)
Filed on Apr. 11, 2022, as Appl. No. 17/658,679.
Prior Publication US 2023/0325088 A1, Oct. 12, 2023
Int. Cl. G06F 3/06 (2006.01); G06F 12/06 (2006.01); G06F 12/08 (2016.01); G06F 12/0897 (2016.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0652 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 12/06 (2013.01); G06F 12/0897 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method performed in a system comprising a local memory area, the method comprising:
receiving, by a transaction queue, an invalidation command comprising a memory location indicator, wherein the invalidation command instructs the invalidation of data stored at physical addresses in the local memory area corresponding to the memory location indicator wherein the local memory area is a first cache memory;
precluding the data stored at the physical addresses from being written to a main memory in response to the invalidation command; and
precluding the data stored at the physical addresses from being written to a second cache memory, wherein the second cache memory is a lower level cache memory than the first cache memory.