US 11,914,864 B2
Storage device and method of data management on a storage device
Jing Yang, San Jose, CA (US); Jingpei Yang, San Jose, CA (US); Rekha Pitchumani, Oak Hill, VA (US); and Sungwook Ryu, Palo Alto, CA (US)
Assigned to Samsung Electronics Co., Ltd., Yongin-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 20, 2021, as Appl. No. 17/408,031.
Claims priority of provisional application 63/217,735, filed on Jul. 1, 2021.
Prior Publication US 2023/0004303 A1, Jan. 5, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0613 (2013.01) [G06F 3/0635 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A storage device comprising:
non-volatile memory;
a storage controller comprising:
a first controller processor connected to the non-volatile memory; and
a second controller processor connected to the non-volatile memory; and
shared memory to store a mapping table, the shared memory being connected to the first controller processor and the second controller processor,
wherein the first controller processor is configured to make a first update to the mapping table based on a first command, and the second controller processor is configured to make a second update to the mapping table based on a second command, wherein the first update includes storing a first mapping of a first logical address to a first physical address, and the second update includes storing a second mapping of a second logical address to a second physical address,
wherein the storage controller is configured to change a power mode of the first controller processor from a first power mode to a second power mode based on an input/output (TO) intensity, and
wherein an IO request directed for the first controller processor is transferred to the second controller processor, and data corresponding to the IO request is stored at the non -volatile memory based on information in the mapping table;
wherein the storage controller is further configured to change a first number of channels associated with the first controller processor and a second number of channels associated with the second controller processor.