US 11,914,756 B2
Data protection in computer processors
Steven Jeffrey Wallach, Dallas, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 22, 2021, as Appl. No. 17/383,123.
Application 17/383,123 is a continuation of application No. 16/054,913, filed on Aug. 3, 2018.
Prior Publication US 2021/0350030 A1, Nov. 11, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 21/71 (2013.01); G06F 9/30 (2018.01); G06F 21/60 (2013.01); G06F 12/14 (2006.01); G06F 12/0802 (2016.01)
CPC G06F 21/71 (2013.01) [G06F 9/30178 (2013.01); G06F 12/0802 (2013.01); G06F 12/1408 (2013.01); G06F 21/602 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/402 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer system, comprising:
a memory; and
a processor coupled with the memory, the processor having:
a cache;
a register;
an execution unit; and
a first logic circuit configured to:
convert scrambled data in the cache into unscrambled data in response to an instruction configured to load data from the memory into the register, wherein the data from the memory is in the cache as the scrambled data; and
load the unscrambled data into the register in response to the instruction.