US 11,914,530 B2
Memory having internal processors and data communication methods in memory
Robert M. Walker, Raleigh, NC (US); Dan Skinner, Boise, ID (US); Todd A. Merritt, Boise, ID (US); and J. Thomas Pawlowski, Boise, ID (US)
Filed by Lodestar Licensing Group, LLC, Evanston, IL (US)
Filed on Jul. 14, 2022, as Appl. No. 17/864,629.
Application 15/288,077 is a division of application No. 12/603,376, filed on Oct. 21, 2009, granted, now 9,477,636, issued on Oct. 25, 2016.
Application 17/864,629 is a continuation of application No. 15/288,077, filed on Oct. 7, 2016, granted, now 11,403,240.
Prior Publication US 2022/0350760 A1, Nov. 3, 2022
Int. Cl. G06F 13/16 (2006.01); G06F 12/0813 (2016.01); G06F 15/78 (2006.01); G06F 3/06 (2006.01); G06F 9/30 (2018.01); G06F 13/40 (2006.01)
CPC G06F 13/1673 (2013.01) [G06F 3/0613 (2013.01); G06F 3/0625 (2013.01); G06F 3/0659 (2013.01); G06F 3/0683 (2013.01); G06F 9/3001 (2013.01); G06F 9/30043 (2013.01); G06F 12/0813 (2013.01); G06F 13/4068 (2013.01); G06F 15/7821 (2013.01); G06F 3/067 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A memory comprising:
a memory array;
a plurality of internal processors of the memory embedded on the memory array, wherein a first internal processor of the plurality is configured to execute at least part of an instruction to produce a result; and
a buffer coupled to the memory array and the first internal processor, wherein the buffer is configured to concurrently retrieve data from the memory array and store the result to the memory array.