US 11,914,524 B2
Latency management in synchronization events
Adrian Montero, Austin, TX (US); Huzefa Sanjeliwala, Austin, TX (US); Paul Kitchin, Austin, TX (US); Prarthna Santhanakrishnan, Austin, TX (US); Conrado Blasco, San Mateo, CA (US); and Pradeep Kanapathipillai, Campbell, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Mar. 1, 2022, as Appl. No. 17/684,231.
Prior Publication US 2023/0281133 A1, Sep. 7, 2023
Int. Cl. G06F 12/1036 (2016.01); G06F 9/30 (2018.01); G06F 9/455 (2018.01)
CPC G06F 12/1036 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30047 (2013.01); G06F 9/30087 (2013.01); G06F 9/45558 (2013.01); G06F 2009/45562 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method for managing memory accesses, implemented at a respective processor of one or more processors that are configured to execute one or more virtual machines, comprising:
receiving a request for initiating a synchronization event; and
in response to the request:
identifying a subset of speculative memory access requests in one or more memory access request queues;
automatically, in accordance with the identifying, purging translations associated with the subset of speculative memory access requests; and
initiating the synchronization event,
wherein the respective processor includes a memory management unit (MMU) configured to manage the one or more memory access request queues, the method further comprising:
in response to the request, generating by the respective processor a purge instruction to purge translations of the subset of speculative memory access requests, wherein the MMU identities the subset of speculative memory access requests in the one or more memory access queues and purges the translations associated with the subset of speculative memory access requests.