CPC G06F 12/10 (2013.01) [G06F 12/1027 (2013.01); G06F 12/14 (2013.01); G06F 2212/1032 (2013.01)] | 16 Claims |
1. An apparatus comprising:
memory access control circuitry to perform a translation of a virtual address of a memory access to a physical address associated with a memory location to be accessed,
wherein:
the memory access control circuitry is arranged to access a page table when performing the translation;
the page table comprises a descriptor comprising translation parameters for the translation;
the descriptor further comprises an integrity check value, wherein the integrity check value is dependent on the translation parameters;
the memory access circuitry comprises integrity verification value calculation circuitry to generate the integrity check value, wherein the integrity verification value calculation circuitry comprises authenticated integrity check value generation circuitry to generate the integrity check value in dependence on a private key; and
the authenticated integrity check value generation circuitry is arranged to generate the integrity check value in response to more-privileged software and is arranged not to generate the integrity check value in response to less-privileged software.
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