US 11,914,522 B2
Verifying address translation integrity
Jason Parker, Sheffield (GB)
Assigned to Arm Limited, Cambridge (GB)
Appl. No. 17/907,206
Filed by ARM LIMITED, Cambridge (GB)
PCT Filed Feb. 8, 2021, PCT No. PCT/GB2021/050279
§ 371(c)(1), (2) Date Sep. 23, 2022,
PCT Pub. No. WO2021/198636, PCT Pub. Date Oct. 7, 2021.
Claims priority of application No. 2004744 (GB), filed on Mar. 31, 2020.
Prior Publication US 2023/0109159 A1, Apr. 6, 2023
Int. Cl. G06F 12/10 (2016.01); G06F 12/1027 (2016.01); G06F 12/14 (2006.01)
CPC G06F 12/10 (2013.01) [G06F 12/1027 (2013.01); G06F 12/14 (2013.01); G06F 2212/1032 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An apparatus comprising:
memory access control circuitry to perform a translation of a virtual address of a memory access to a physical address associated with a memory location to be accessed,
wherein:
the memory access control circuitry is arranged to access a page table when performing the translation;
the page table comprises a descriptor comprising translation parameters for the translation;
the descriptor further comprises an integrity check value, wherein the integrity check value is dependent on the translation parameters;
the memory access circuitry comprises integrity verification value calculation circuitry to generate the integrity check value, wherein the integrity verification value calculation circuitry comprises authenticated integrity check value generation circuitry to generate the integrity check value in dependence on a private key; and
the authenticated integrity check value generation circuitry is arranged to generate the integrity check value in response to more-privileged software and is arranged not to generate the integrity check value in response to less-privileged software.