US 11,914,520 B2
Separate read-only cache and write-read cache in a memory sub-system
Dhawal Bavishi, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 23, 2022, as Appl. No. 17/678,959.
Application 17/678,959 is a continuation of application No. 16/289,421, filed on Feb. 28, 2019, granted, now 11,288,199.
Prior Publication US 2022/0179798 A1, Jun. 9, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 12/0893 (2016.01); G06F 12/0862 (2016.01)
CPC G06F 12/0893 (2013.01) [G06F 12/0862 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/602 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
retrieving data associated with a memory access workload of an application from a backing store; and
storing, based on the memory access workload, the data associated with the memory access workload and retrieved from the backing store in a memory device comprising a cache of a first type and a cache of second type, wherein data associated with sequential read operations comprising a plurality of read requests received in order and directed to at least one of a same memory address or sequential memory addresses is stored at the cache of the first type, and wherein data associated with write and read operations is stored at the cache of the second type.