US 11,914,517 B2
Method and apparatus for monitoring memory access traffic
Sergey Blagodurov, Seattle, WA (US); Marko Scrbak, Austin, TX (US); and Brandon K. Potter, Austin, TX (US)
Assigned to ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Nov. 11, 2020, as Appl. No. 17/094,989.
Claims priority of provisional application 63/083,483, filed on Sep. 25, 2020.
Prior Publication US 2022/0100668 A1, Mar. 31, 2022
Int. Cl. G06F 12/08 (2016.01); G06F 12/0877 (2016.01); G06F 12/0815 (2016.01)
CPC G06F 12/0877 (2013.01) [G06F 12/0815 (2013.01); G06F 2212/621 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data processing system comprising:
a host processor;
a memory coupled to the host processor;
a scalable data fabric operatively coupled to the host processor and comprising hardware control logic operative to:
track a number of cache line accesses to a page of main memory associated with one or more data fabric attached remote memory devices; and
produce spike indication data, that is accessible by a memory scheduler, that indicates a spike in cache line accesses to a given page of main memory associated with the one or more data fabric attached remote memory devices.